Page buffer circuit and memory device including the same
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United States of America Patent
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Dec 12, 2023
Grant Date -
Jul 13, 2023
app pub date -
Mar 23, 2023
filing date -
Jul 17, 2020
priority date (Note) -
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status (Latency Note)
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Abstract
Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.
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