High performance transistors with SiGe strain
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United States of America Patent
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Sep 11, 2007
Grant Date -
Aug 31, 2006
app pub date -
Feb 25, 2005
filing date -
Feb 25, 2005
priority date (Note) -
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Abstract
A preferred embodiment of the invention comprises a semiconductor device having stress in the source/drain channel. The device comprises a substrate having a lattice constant greater than or equal to silicon and a first layer on the substrate, wherein the first layer has a lattice constant greater than the substrate. Alternative embodiments include a second layer formed on the first layer. The second layer has a lattice constant less than the first layer. Preferably, the second layer underlies a gate electrode and at least a portion of a sidewall spacer. Still other embodiments include a recess for inducing stress in the source/drain channel.
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