Mesh interconnected array in a fault-tolerant computer system
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United States of America Patent
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Apr 21, 1998
Grant Date -
N/A
app pub date -
Jun 6, 1996
filing date -
Jun 6, 1996
priority date (Note) -
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Abstract
Bus interface units (BIUs)(54) perform fault detection, identification, and reconfiguration for all information transfers between redundant central processing units (CPUs)(56) and memory or input/output (I/O)(57A-C) in a mesh interconnected array of a highly reliable fault-tolerant computer system. Errors are detected by self-checking within the BIUs, signal parity checks by the BIUs, cross channel comparisons, and mesh transaction assessments. Fault identification and mesh reconfiguration for the mesh is performed such that no faulty unit remains active in decision making after reconfiguration, and the number of good units isolated during reconfiguration is minimized.
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