Data latch circuit and driving method thereof
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United States of America Patent
Stats
-
Dec 9, 2003
Grant Date -
Jul 5, 2001
app pub date -
Dec 15, 2000
filing date -
Dec 22, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A data latch circuit of the present invention, which corresponds to the semiconductor circuit, is provided with a master flip-flop and a slave flip-flop. The master flip-flop fetches a first signal in response to a first clock signal, holds first data corresponding to the first signal as binary data in response to the first clock signal, and also outputs the first data as a second signal. The slave flip-flop fetches the second signal in response to an OR-gated result obtained between the first clock signal and either one or a plurality of second clock signals, and the slave flip-flop holds second data corresponding to the second signal in response to the OR-gated result, and also the slave flip-flop outputs a third signal corresponding to the second data.
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