Semiconductor integrated circuit and method for testing the same
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United States of America Patent
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Mar 25, 2008
Grant Date -
Sep 15, 2005
app pub date -
Jul 29, 2004
filing date -
Mar 10, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and semiconductor integrated circuit in which a receiver receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmission processing on the basis of the clock signal, and having a loop back function of supplying data output from the transmitter to the receiver for test. The receiver capable of executing control so as to make a phase of the input data coincide with that of a recovery clock.
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