Method of fabricating semiconductor device including planarizing conductive layer using parameters of pattern density and depth of trenches
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United States of America Patent
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Jun 15, 2010
Grant Date -
Aug 23, 2007
app pub date -
Dec 7, 2006
filing date -
Feb 9, 2006
priority date (Note) -
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Abstract
A method of fabricating a semiconductor device includes forming a conductive layer on an insulating layer having a plurality of trenches on a semiconductor substrate, such that the conductive layer fills in the plurality of trenches formed in the insulating layer, and calculating a target eddy current value to measure an end point using parameters of a pattern density and a depth of the trenches. The method further includes planarizing the conductive layer and measuring eddy current values on the conductive layer using an eddy current monitoring system, and stopping the planarization when the measured eddy current value reaches the target eddy current value to form a planarized conductive layer having a target height on the insulating layer.
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