Integrated circuit design flow with capacitive margin

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United States of America Patent

PATENT NO 6810505
APP PUB NO 20040010761A1
SERIAL NO

10192989

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method of designing an integrated circuit includes receiving as input a representation of a circuit design and a margin factor and scaling a parameter value in the circuit design by the margin factor to account for coupling in the circuit design. The margin factor advantageously reduces the number of iterations in the design flow and avoids the necessity of cross-talk analysis.

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Patent Owner(s)

  • BELL SEMICONDUCTOR, LLC

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Al-Dabagh, Maad A Sunnyvale, CA 5 83
Huynh, Duc Van San Jose, CA 2 18
Molina, Jr Ruben San Ramon, CA 3 21
Tetelbaum, Alexander Hayward, CA 52 514

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