Memory device capable of refreshing data using buffer and refresh method thereof
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United States of America Patent
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Aug 28, 2007
Grant Date -
Apr 27, 2006
app pub date -
Oct 24, 2005
filing date -
Oct 25, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit memory device includes a plurality of memories and a refresh controller within a memory system. The refresh controller is configured to generate a refresh request signal. The plurality of memories includes a plurality of banks of memory responsive to the refresh request signal. An additional memory includes a buffer unit configured to generate a refresh indication signal to a first one of the plurality of banks of memory and to receive buffer write data addressed to the first one of the plurality of banks of memory in response to receiving a refresh-access interrupt signal from the one of the plurality of banks of memory. The plurality of banks of memory and the buffer unit may be separate DRAM chips.
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