Molds configured to pattern masses associated with semiconductor constructions
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United States of America Patent
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Jan 24, 2006
Issued Date -
N/A
app pub date -
Jun 12, 2003
filing date -
Mar 12, 2002
priority date (Note) -
Expired
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Abstract
The invention includes methods of forming patterns in low-k dielectric materials by contact lithography. In a particular application, a mold having a first pattern is pressed into a low-k dielectric material to form a second pattern within the material. The second pattern is substantially complementary to the first pattern. The mold is then removed from the low-k dielectric material. The invention also includes a method of forming a mold; and includes a mold configured to pattern a mass over a semiconductor substrate during contact lithography of the mass.
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