Defective block handling in a flash memory device
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United States of America Patent
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May 22, 2007
Grant Date -
Nov 16, 2006
app pub date -
May 12, 2005
filing date -
May 12, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
A method and circuit that remaps, to a single redundant memory block, defective rows from amongst a plurality of defective memory blocks. The circuit determines which rows of each memory block is defective and maps any further access to those rows to the redundant memory block. During an erase operation of the remapped memory rows, the selected rows are biased with an erase voltage, the source line and tub are biased at some high voltage that can be greater than V.sub.CC. The unselected word lines are biased at a voltage that is substantially equal to the substrate voltage.
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