Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
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United States of America Patent
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Sep 25, 2007
Grant Date -
Sep 28, 2006
app pub date -
Mar 23, 2005
filing date -
Mar 23, 2005
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Abstract
A method of fabricating integrated circuitry includes depositing a spin-on-dielectric over a semiconductor substrate. The spin-on-dielectric comprises a polysilazane. Only some of the polysilazane is etched from the semiconductor substrate. Such etching comprises exposure to an etching fluid comprising at least one of a) an aqueous fluid having a pH greater than 7.0, or b) a basic fluid solution. After the etching, remaining spin-on-dielectric comprising polysilazane is annealed effective to form an annealed dielectric which is different in composition from the spin-on-dielectric, and preferably having a dielectric constant k which is different from that of the initially deposited spin-on-dielectric.
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