Method for providing an on-chip variation determination and integrated circuit utilizing the same
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United States of America Patent
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May 30, 2017
Grant Date -
Feb 25, 2016
app pub date -
Jul 29, 2015
filing date -
Aug 19, 2014
priority date (Note) -
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Abstract
A method for providing an on-chip variation determination and an integrated circuit utilizing the same are provided. The method includes: outputting, by a launch register circuit, a test data to the capture register circuit according to the first clock; receiving, by a capture register circuit, the test data from the launch register circuit according to the second clock; adjusting, by a control circuit, a first number of a first chain of delay elements to generate the first clock and a second number of a second chain of delay elements for the capture register circuit to just capture the test data to generate the second clock; and determining, by the control circuit, a path delay between the launch register circuit and the capture register circuit based on the first number of the first chain of delay elements and the second number of the second chain of delay elements.
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