LOCK AND KEY STRUCTURE FOR THREE-DIMENTIONAL CHIP CONNECTION AND PROCESS THEREOF
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United States of America Patent
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Jul 28, 2009
Grant Date -
Aug 6, 2009
app pub date -
Feb 6, 2008
filing date -
Feb 6, 2008
priority date (Note) -
Granted
status (Latency Note)
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Abstract
A method positions a first wafer with respect to a second wafer such that key studs on the first wafer are fit (positioned) within lock openings in the second wafer. The key studs contact conductors within the second wafer. The edges of the first wafer are tacked to the edges of the second wafer. Then the wafers are pressed together and heat is applied to bond the wafers together. One feature of embodiments herein is that because the lock openings extend through an outer oxide (instead of a polyimide) the first wafer can be attached to the second wafer by using processing that occurs in the middle-of-the-line (MOL).
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