Structure and method for failure analysis in a semiconductor device
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United States of America Patent
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Dec 23, 2008
Grant Date -
Jun 8, 2006
app pub date -
Nov 30, 2005
filing date -
Dec 7, 2004
priority date (Note) -
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Abstract
In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a first direction; and bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a second direction, wherein the bitline structures are configured in different patterns in each of the plurality of analytic fields.
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