Charge pump clock for non-volatile memories
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United States of America Patent
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Feb 5, 2008
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app pub date -
May 10, 2006
filing date -
Apr 26, 2004
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Abstract
A charge pump clock circuit for a memory device generates pump clock signals at an adaptive rate. Clock edges are generated at a minimum of T.sub.D seconds apart so long as address transitions do not exceed a pre-determined limit. However, if address changes are occurring more frequently than this limit, i.e., 1/(2*T.sub.D), then clock edges will be generated at a rate that is proportional to the rate of address changes, where T.sub.D is approximately half of the address period. Two logic rules are implemented in hardware or equivalent software to make the clock signal adjustments.
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