Dynamic semiconductor memory device and power saving mode of operation method of the same
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United States of America Patent
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Jan 23, 2007
Grant Date -
Jul 28, 2005
app pub date -
Dec 16, 2004
filing date -
Dec 31, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode setting portion receives a mode setting code applied from an external portion to generate a power saving mode control signal for a power saving mode of operation responsive to a mode setting command. An address control portion decodes an address applied from an external portion or a refresh address to select one of the plurality of the word lines during a normal mode operation. The address control portion also selects a predetermined number of bits of the address during a power saving mode of operation. The semiconductor memory device, therefore extends the refresh cycle while reducing the refresh time resulting in a lower power consumption.
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