Method of design and fabrication of integrated circuits using regular arrays and gratings

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6818389
APP PUB NO 20020045136A1
SERIAL NO

09952185

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Abstract

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A circuit fabrication and lithography process utilizes a mask including dense repetitive structures of features that result in a wide array of fine densely populated features on the exposed substrate film. Following this, a trimming procedure is performed to remove any unwanted fine patterned features providing multiple trimmed patterns on the substrate. An optional final step adds additional features as well as the interconnect features thus forming a circuit pattern. In this manner, all fine features may be generated using the exact same density of intensity patterns, and therefore, maximum consistency between features is established without the need for optical proximity correction. The secondary exposures are substantially independent from the initial dense-feature exposure in that the exposure of one set of features and the subsequent exposure of another set of features result in separate independent resist or masking layer reactions, thus minimizing corner rounding, line end shortening and other related spatial frequency effects and unwanted exposure memory effects.

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Patent Owner(s)

  • MASSACHUSETTS INSTITUTE OF TECHNOLOGY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fritze, Michael Acton, MA 8 301
Tyrrell, Brian Riverside, RI 17 522

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