Nonvolatile semiconductor memory device having row decoder supplying a negative potential to word lines during erase mode
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United States of America Patent
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Oct 21, 1997
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N/A
app pub date -
Feb 20, 1996
filing date -
Jul 25, 1991
priority date (Note) -
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Abstract
A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.
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