Methods and systems for dynamically selecting word line off times and/or bit line equalization start times in memory devices
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United States of America Patent
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Feb 13, 2007
Grant Date -
Jun 9, 2005
app pub date -
Nov 18, 2004
filing date -
Dec 4, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Methods for controlling the timing of a pre-charge operation in a memory device are provided. In embodiments of the present invention, the timing may be controlled by dynamically selecting a word line off time based on information about a number of column cycles. This may be accomplished, for example, by routing a word line disable signal via one of a first plurality of delay paths. The methods may further include dynamically selecting a bit line equalization start time based on the information about the number of column cycles. This may be accomplished, for example, by routing a bit line equalization start signal via one of a second plurality of delay paths. Pursuant to still further embodiments of the present invention, systems for controlling timing in a memory device are provided which include a control circuit that is configured to select a word line off time from a plurality of word line off times in response to a word line signal and information about a number of column cycles.
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