Systems and methods for an ECC architecture with prioritized task queues

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United States of America

PATENT NO 11204829
APP PUB NO 20200310911A1
SERIAL NO

16364360

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Abstract

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Systems, apparatus and methods are provided for an error correction code (ECC) architecture with reduced decoding latency in error control. An apparatus may comprise control circuitry configured to receive a status report that a decoding task has failed, determine that a higher priority is needed for a re-decoding task, generate a NAND read task having a second priority level higher than a first priority level of the failed decoding task, and generate an ECC re-decoding task having the second priority level.

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Patent Owner(s)

  • INNOGRIT TECHNOLOGIES CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Jie Milpitas, US 933 4890
Fu, Bo San Jose, US 57 324
Wu, Zining Los Altos, US 323 4496
Zhu, Xiaoming San Jose, US 33 273

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