Method for forming a chip package
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United States of America Patent
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-
Aug 7, 2007
Grant Date -
Jan 27, 2005
app pub date -
Aug 16, 2004
filing date -
Jul 17, 2003
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A chip package is formed which has an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another to permit a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggered in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.
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