MIS semiconductor device with sloped gate, source, and drain regions

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United States of America Patent

PATENT NO 6417543
SERIAL NO

09641559

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Abstract

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The invention is concerned with the fabrication of a MIS semiconductor device of high reliability by using a low-temperature process. Disclosed is a method of fabricating a MIS semiconductor device, wherein doped regions are selectively formed in a semiconductor substrate or a semiconductor thin film, provisions are then made so that laser or equivalent high-intensity light is radiated also onto the boundaries between the doped regions and their adjacent active region, and the laser or equivalent high-intensity light is radiated from above to accomplish activation.

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Patent Owner(s)

  • SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Takemura, Yasuhiko Kanagawa, JP 581 31440
Yamazaki, Shunpei Tokyo, JP 7291 226813

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