Importance

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Abstract

An integrated multi-processor system with clusters of processors on a high speed split transaction bus uses a transaction acknowledge (TACK), by a target device in response to receiving a request from a master device on the bus. The master and target devices connect to the bus via a global bus interface with FIFO registers acting as buffers, and the target interface includes a TACK generator that flips the state of the global bus' TACK line upon determining that a broadcast request is addressed to its target device. A bus idle default device (BIDD) generates a TACK signal when no device is on the bus, and also detects the absence of any TACK response by monitoring the state of the TACK line, thereby indicating that a master device bus attempted to address a nonexistent target a device. The BIDD then generates a dummy response for the requesting master device with data flags set to invalid data.

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First Claim