Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production
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United States of America
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Jul 26, 2011
Issued Date -
N/A
app pub date -
Jul 29, 2009
filing date -
Jul 29, 2009
priority date (Note) -
Withdrawn
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Abstract
A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.
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