Semiconductor memory device, memory system including the same and operating method thereof
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United States of America Patent
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Dec 15, 2015
Grant Date -
Apr 30, 2015
app pub date -
Mar 19, 2014
filing date -
Oct 25, 2013
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Abstract
A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for generating program and erase voltages and applying the program and erase voltages to the plurality of memory cells when program and erase operations are performed on the plurality of memory cells, and a control logic suitable for controlling the peripheral circuit unit during the program and erase operations and counting a pulse number of the program and erase voltages to store a resultant count number as status data.
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