DPLL circuit having holdover function
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United States of America Patent
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Feb 12, 2008
Grant Date -
Aug 9, 2007
app pub date -
Jul 18, 2006
filing date -
Feb 8, 2006
priority date (Note) -
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Abstract
The invention relates to a digital synchronization network, and provides a DPLL circuit having a holdover function that generates a high-precision reference clock with a temperature correction to perform a free-running frequency control at a holdover time. In a holdover mode of the DPLL circuit using a DDS, the DPLL circuit having a holdover function adds a correction value calculated from a temperature characteristic of a slave oscillator to a fixed DDS control value during a detection of a holdover, thereby changing the DDS control value according to the temperature characteristic.
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