Architecture to support tanh and sigmoid operations for inference acceleration in machine learning

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United States of America

PATENT NO 11966857
APP PUB NO 20210248497A1
SERIAL NO

17223921

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Abstract

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A processing unit to support inference acceleration for machine learning (ML) comprises an inline post processing unit configured to accept and maintain one or more lookup tables for performing a tanh and/or sigmoid operation/function. The inline post processing unit is further configured to accept data from a set of registers configured to maintain output from a processing block instead of streaming the data from an on-chip memory (OCM), perform the tanh and/or sigmoid operation on each element of the data from the processing block on a per-element basis via the one or more lookup tables, and stream post processing result of the per-element tanh and/or sigmoid operation back to the OCM after the tanh and/or sigmoid operation is complete.

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Patent Owner(s)

  • MARVELL ASIA PTE, LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Chia-Hsin Santa Clara, US 103 462
Hanebutte, Ulf Gig Harbor, US 23 45
Sodani, Avinash San Jose, US 90 618

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