DRAM cell configuration and fabrication method

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6504200
APP PUB NO 20020079527A1
SERIAL NO

09951243

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions are located below the word lines and between adjacent trenches. The capacitors are linked with the upper source/drain regions. Conductive structures that surround the word lines from the top and the sides while being insulated from the word lines and bordering on the upper source/drain regions can link the upper source/drain regions with the capacitors.

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Patent Owner(s)

  • POLARIS INNOVATIONS LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Schlosser, Till Dresden, DE 46 891
Sell, Bernhard Dresden, DE 109 1086
Willer, Josef Riemerling, DE 132 2904

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