Dual stressed SOI substrates

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7262087
APP PUB NO 20060125008A1
SERIAL NO

10905062

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Abstract

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The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si.sub.3N.sub.4.

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Patent Owner(s)

  • GLOBALFOUNDRIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chidambarrao, Dureseti Weston, CT 255 6093
Dokumaci, Omer H Wappingers Falls, NY 103 2563
Doris, Bruce B Brewster, NY 796 13219
Gluschenkov, Oleg Poughkeepsie, NY 263 3542
Zhu, Huilong Poughkeepsie, NY 688 12401

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