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Abstract

In the invention, it becomes possible to extract all clock information data processing data by simultaneously comparing first, second and third voltage levels to each data bit in clocked time increments wherein the magnitude of the increments is such that each binary data bit is in two of the three voltage levels and all data bits change each clock cycle, so that reconstructed signals of the binary information only may then be assembled based on a signal amplitude that is greater than a low threshold value that is less than the transition between the first and the second of the voltage levels and is less than a high threshold that is greater than the transition between the second and the third voltage levels. The reconstructed data signals are further shaped to be precise in timing, free of skewing and within the system clock.

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First Claim