Tunable negative bitline write assist and boost attenuation circuit
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United States of America Patent
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Dec 19, 2017
Issued Date -
N/A
app pub date -
Sep 15, 2016
filing date -
Jan 12, 2015
priority date (Note) -
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Abstract
An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
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