Area efficient memory cell read disturb mitigation

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11804262
APP PUB NO 20220406371A1
SERIAL NO

17350973

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.

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Patent Owner(s)

  • NVIDIA CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gotterba, Andreas Jon Santa Clara, US 3 0
Gupta, Lalit Fremont, US 51 244
Sywyk, Stefan P San Jose, US 20 434
Wang, Jesse Santa Clara, US 9 163

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