Memory device and method for fabricating the same
Number of patents in Portfolio can not be more than 2000
United States of America
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Dec 28, 2021
Grant Date -
Jul 1, 2021
app pub date -
Dec 27, 2019
filing date -
Dec 27, 2019
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.
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