Delay stage for a clock generator
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United States of America Patent
Stats
-
Apr 12, 1983
Grant Date -
N/A
app pub date -
Sep 10, 1980
filing date -
Sep 10, 1980
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A delay stage (30,50) receives input signals at input terminal (16) and power from power terminals (12, 14). A detector circuit (30) is connected between power terminals (12, 14) and to the input terminal (16) for receiving the input signal and for generating a detection signal upon detecting a predetermined level of the input signal. A buffer circuit (50) is connected between the power terminals (12, 14) and to the detector circuit (30) for receiving the detection signal while not capacitively loading the detector circuit (30).
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