Importance

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Abstract

A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.

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First Claim