Methods and devices for fault tolerant quantum gates

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United States of America Patent

PATENT NO 11460876
SERIAL NO

16509219

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A method includes obtaining a plurality of entangled qubits, with high fault tolerance, represented by a lattice structure. The lattice structure includes a plurality of contiguous lattice cells. A first subset of the plurality of entangled qubits defines a first plane, and a second subset of the plurality of entangled qubits defines a second plane that is parallel to and offset from the first plane. The plurality of entangled qubits includes a defect qubit that is entangled with at least one face qubit on the first plane and at least one edge qubit on the second plane.

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Patent Owner(s)

  • PSIQUANTUM CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bombin, Palomo Hector Kyoto, JP 4 15
Brown, Benjamin Palo Alto, US 25 136
Nickerson, Naomi San Francisco, US 17 63

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