Memory with read circuit for current-to-voltage slope characteristic-based sensing and method
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United States of America Patent
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Jul 5, 2022
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N/A
app pub date -
May 12, 2021
filing date -
May 12, 2021
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Abstract
Disclosed is a memory structure including an array of memory cells and a read circuit. The read circuit includes two registers configured to capture and store two different digital-to-analog converter (DAC) codes, which correspond to two different reference currents that approximate two different output currents generated on a bitline during consecutive single-ended current sensing processes directed to the same selected memory cell but using different input voltages. Optionally, the read circuit can also include a current-voltage (I-V) slope calculator, which uses the two different DAC codes to calculate an I-V slope characteristic of the selected memory cell, and a bit generator, which performs a comparison of the I-V slope characteristic and a reference I-V slope characteristic and based on results of the comparison, generates and outputs a bit with a logic value that represents the data storage state of the selected memory cell. Also disclosed is an associated method.
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Patent Owner(s)
- GLOBALFOUNDRIES U.S. INC.
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Kirihata, Toshiaki | Poughkeepsie, US | 150 | 2341 |
Min, Byoung-Woon B | Halfmoon, US | 1 | 0 |
Nour, Mohamed A | Ballston Spa, US | 1 | 0 |
Paliwoda, Peter C | Saratoga Springs, US | 1 | 0 |
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