Method for forming a strained transistor by stress memorization based on a stressed implantation mask
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United States of America Patent
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Jun 21, 2011
Grant Date -
Jan 31, 2008
app pub date -
May 9, 2007
filing date -
Jul 31, 2006
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Abstract
By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.
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