Semiconductor package with conductor impedance selected during assembly
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United States of America Patent
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-
Nov 7, 2006
Grant Date -
Oct 30, 2003
app pub date -
Apr 10, 2003
filing date -
Dec 29, 1999
priority date (Note) -
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Abstract
A semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and an available ground conductor. Conductors in the auxiliary or second plane substantially overlay the primary signal conductors in the first plane, and the impedance of any lead or lead pair is arbitrarily set at the assembly process by connecting the auxiliary conductors to ground or by leaving them floating. Differential pairs of signal conductors, either odd or even mode are set by connecting the auxiliary conductors to a ground contact.
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