Memory apparatus and method of operation using state bit-scan dependent ramp rate for peak current reduction during program operation

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United States of America Patent

PATENT NO 11521686
APP PUB NO 20220319605A1
SERIAL NO

17218498

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Abstract

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A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.

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Patent Owner(s)

  • SANDISK TECHNOLOGIES LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hsu, Hua-Ling Fremont, US 9 49
Lien, Yu-Chung San Jose, US 72 73
Tseng, Huai-Yuan San Ramon, US 107 544
Zhang, Fanglin Fremont, US 17 198

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