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Abstract

An ECL multiplexing circuit (20) includes two differential pairs (21 and 22) for receiving first and second ECL level input signals, emitter-follower output transistors (27 and 28), and a differential pair (31 and 32) for receiving differential clock signals. The differential clock signals control which of the two differential pairs (21 and 22) is coupled to the emitter-follower output transistors (27 and 28). The ECL level input signals that control a logic state of the output signals is determined by the logic state of the clock signals. The ECL multiplexing circuit (20) receives non-overlapping clock signals and is used in a quadrature frequency divide-by-two circuit (40) to divide a frequency of an input clock signal by two.

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