Apparatus and method for performance state matching between source and target processors based on interprocessor interrupts

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United States of America Patent

PATENT NO 11775336
APP PUB NO 20210191753A1
SERIAL NO

16723691

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Abstract

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Apparatus, method, and machine-readable medium to provide performance state matching between source and target processors based on inter-processor interrupts. An exemplary apparatus includes a target processor to execute a receiving task at a first performance level and a source processor to execute a sending task at a second performance level higher than the first performance level. The sending task is to store interrupt routing data indicating a pairing between the sending task and the receiving task into a memory location and that the sending task is to dispatch work to be processed by the receiving task. The apparatus further includes a performance management unit to detect the pairing between the sending task and the receiving task based on the interrupt routing data and responsively adjust the performance level of the target processor from the first performance level to the second performance level based, at least in part, on the pairing.

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Patent Owner(s)

  • INTEL CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Pan, Jacob Portland, US 4 10
Pandruvada, Srinivas Beaverton, US 7 22
Raj, Ashok Portland, US 62 365

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