SOI structure for signal isolation and linearity
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United States of America Patent
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May 17, 2016
Grant Date -
Dec 18, 2014
app pub date -
Sep 2, 2014
filing date -
Jan 13, 2012
priority date (Note) -
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Abstract
Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.
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