Memory with DQS pulse control circuitry, and associated systems, devices, and methods
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United States of America Patent
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Dec 19, 2023
Grant Date -
May 11, 2023
app pub date -
Nov 10, 2021
filing date -
Nov 10, 2021
priority date (Note) -
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Abstract
Memory with DQS pulse control circuitry is disclosed herein. In one embodiment, a memory device comprises a DQS terminal and circuitry operably coupled to the DQS terminal. The DQS terminal is configured to receive an external DQS signal including a first pulse having a first width. In turn, the circuitry is configured to generate a second pulse based at least in part on the first pulse and output an internal DQS signal including the second pulse. The second pulse can have a second width greater than the first width. In some embodiments, the external DQS signal can further include a third pulse having a third width greater than the second width. In such embodiments, the circuitry can be further configured to generate and output a fourth pulse based at least in part on the third pulse that has a fourth width equivalent to the third width.
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