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Abstract

An input data signal string I is temporarily stored in an input register, and is input to a parallel adder operating according to the instruction of a control unit. The control unit designates an address of a ROM storing a check matrix H, and obtains information about locations of '1s' in a specific column of the check matrix corresponding to a current input data bit. The ROM instructs selectors SEL1#1 SEL1#CW to select from a register reg(M) bits corresponding to rows in which the check matrix value is 1 for the specified matrix column and sends the selected values to the adder. Results of the additions and the values output from the reg(M) are selected between for input to the reg(M) through the selectors SEL2#1 SEL2#M. This process is repeated until all the input bits have been processed.

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First Claim