Zero padding apparatus for encoding variable-length signaling information and zero padding method using same
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United States of America Patent
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Jul 11, 2023
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N/A
app pub date -
Mar 15, 2022
filing date -
Feb 27, 2015
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Abstract
A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
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