Importance

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Abstract

Data externally inputted in series are output aligned in parallel for a prefetch operation by a data alignment circuit. In the prefetch operation, sequential odd numbered data are latched in response to a rising data strobe signal and sequential even numbered data are latched in response to a falling data strobe signal. Thereafter, the data are output aligned only in response to the falling data strobe signal. The number of latch circuits is reduced. The data alignment circuit includes: a first latch unit that latches the data in response to the data strobe signal to output first and second alignment signals that are output aligned to the falling edge of the data strobe signal; and a second latch unit that latches the first and second alignment signals at the falling edge of the data strobe signal to output align third and fourth data alignment signals that are aligned to the falling edge of the data strobe signal.

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First Claim