PLL clock generator circuit and clock generation method
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United States of America Patent
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-
Aug 7, 2007
Grant Date -
Mar 18, 2004
app pub date -
Aug 28, 2003
filing date -
Sep 12, 2002
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A clock generator circuit is provided wherein a comparison clock signal is generated by comparing a standard clock signal and an operating clock signal. The comparison clock signal is converted into a current signal. The current signal is converted to multiple current signals and an operating clock signal having multiple varying frequencies is generated based on the multiple current signals.
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