Method for fabricating polysilicon TFT
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United States of America Patent
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May 28, 2002
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N/A
app pub date -
Sep 20, 2000
filing date -
Sep 20, 1999
priority date (Note) -
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Abstract
Fabrication of a polysilicon TFT having a lightly doped drain or offset structure. Fabrication includes forming a semiconductor layer, a gate insulating film, and a gate electrode on a substrate. Then, forming lightly doped impurity regions in the semiconductor layer on both sides of the gate electrode. Next, forming an insulating film having a thickness that gradually becomes thinner away from the gate electrode. Then, forming heavily doped impurity regions in the lightly doped impurity regions in the semiconductor layer on both sides of the gate, resulting in regions with continuously varied impurity concentrations.
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