Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement
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United States of America Patent
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Sep 14, 2010
Grant Date -
May 10, 2007
app pub date -
Sep 25, 2006
filing date -
Mar 25, 2004
priority date (Note) -
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Abstract
A method is disclosed for producing an integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement. The invention also relates to a method for producing aligning marks. During the method, a planarization is carried out before material is removed from an auxiliary indentation.
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